In the field of integrated circuit (IC) devices, electrostatic discharge (ESD) is a known problem that can affect the functioning of IC devices, and even cause permanent damage to such devices. Accordingly, ESD protection is an important aspect of the design of IC devices.
A metal oxide semiconductor field effect transistor (MOSFET) has a parasitic bipolar transistor characteristic that may be used to provide ESD protection. For example, an n-channel MOSFET (NMOS) comprises a parasitic NPN bipolar transistor characteristic. If the drain voltage of the NMOS increases beyond its saturation region, many electron-hole pairs are generated by impact ionizations and the NMOS reaches its avalanche region. Electrons that occur due to impact ionizations flow to the drain of the NMOS (e.g. the collector of the parasitic bipolar transistor), with holes flowing to the substrate (e.g. the base of the parasitic bipolar transistor). When a sufficiently large number of holes have collected in the substrate, the parasitic bipolar transistor switches on and the drain current through the NMOS reaches the snapback region. This ‘snapback’ characteristic within the NMOS transistor is often exploited to provide ESD protection within an IC device. Advantageously, such snapback devices provide a compact solution to ESD protection.
However, such a snapback solution is not suitable for high voltage applications due to the possibility of latch-up of the snapback device occurring, making such a solution unreliable. High voltage applications may be considered to comprise voltage levels higher than 40V. Latch-up is a term used to refer to the inadvertent creation of a low impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper function of the circuit, and requires a power cycle to correct the situation. For example, during normal operation if a pin is biased at 80V, and if an ESD event occurs, then the ESD diode goes into snapback and the voltage across the pin will decrease to 30V. In this case the pin that is biased at 80V if forced to go to 30V and the current from the 80V supply or load is discharge into the ESD diode, causing a latch-up. A latch-up can possibly even lead to the destruction of the MOSFET device due to overcurrent.
Non-snapback devices such as large diode-like structures may alternatively be used for high voltage applications, thereby avoiding the problem of latch-up occurring. However, in order to dissipate the energy required for ESD protection, the size of such non-latch-up devices can be undesirably large. For example, in the case of a diode-like structure, the current capability during an ESD event is directly proportional to the active area of the structure. Typically the current density of such a device is between 50 mA and 100 mA per micrometer of active area length. For an 8 kV HBM (Human Body Model) ESD event, the current peak is 5.33 A. To achieve a high voltage (e.g. >80V) diode, a stack of several stages of medium voltage or low voltage diodes is necessary. For example three stages (60V+15V+15V) of diodes may be stacked in series. However, the greater the number of stages in series, the greater the resistance in series of the whole diode structure. In order to reduce the series resistance, the active area of the stages is required to be increased. Accordingly, a high voltage central diode device is required to be larger than a ‘classical’ ESD diode because it is formed by a stack of diodes to elevate the voltage capability and the area has to be increased in order to keep the series resistance to a safe value (for example lower than 3 ohm). As such, such non-snapback devices are typically required to be undesirably large in order to be able to dissipate the energy required for ESD protection.